Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine

We present an FPGA-based reconfigurable platform called Erlangen Slot Machine (ESM). The main advantages of this platform are: First, the possibility for each module to access peripherals independent from its location through a programmable crossbar, and local SRAM banks for individual modules. This physical design eases the implementation of run-time reconfigurable partial modules and enables an unrestricted relocation of modules on the device. We present our two-board ESM implementation and demonstrate a partially reconfigurable video filter application as well as a relocatable computer game including a dedicated inter-module communication scheme

Defragmenting the Module Layout of a Partially Reconfigurable Device

Modern generations of field-programmable gate arrays (FPGAs) allow for partial reconfiguration. In an online context, where the sequence of modules to be loaded on the FPGA is unknown beforehand, repeated insertion and deletion of modules leads to progressive fragmentation of the available space, making defragmentation an important issue. We address this problem by propose an online and an offline component for the defragmentation of the available space. We consider defragmenting the module layout on a reconfigurable device. This corresponds to solving a two-dimensional strip packing problem. Problems of this type are NP-hard in the strong sense, and previous algorithmic results are rather limited. Based on a graph-theoretic characterization of feasible packings, we develop a method that can solve two-dimensional defragmentation instances of practical size to optimality. Our approach is validated for a set of benchmark instances.Comment: 10 pages, 11 figures, 1 table, Latex, to appear in "Engineering of Reconfigurable Systems and Algorithms" as a "Distinguished Paper

Die Erlangen Slot Machine - Eine partiell rekonfigurierbare FPGA-basierte Computerarchitektur

Partial reconfiguration is a special case of device configuration that allows to change only parts of a hardware circuit at run-time. Only a predefined region of an FPGA is updated while the remainder of the device continues to operate undisturbed. This is especially valuable when a device operates in a mission-critical environment and cannot be disrupted while a subsystem is redefined for performance or flexibility reasons. The triggering of partial reconfiguration can be instigated by user requests, detected changes of environmental factors or operating system scheduling. It offers a novel possibility to dynamically load and execute hardware modules, previously only known for software modules. Partial reconfiguration is useful in increasing the computational flexibility and efficiency by time-sharing the existing memory and logic resources on the device. Using partial reconfiguration, the functionality of a single FPGA is increased, allowing fewer or smaller FPGA devices to be used. Embedded systems using FPGAs supporting partial reconfiguration can be customized in their hardware at run-time with partial reconfiguration. However, the design flow and peripheral I/O architectures of these devices are not ideally suited for run-time reconfigurable application development. Therefore, the benefits of partial reconfiguration used in hardware designs are currently seen as limited. The Erlangen Slot Machine (ESM) is introduced as a new FPGA-based dynamically reconfigurable computer architecture supporting run-time customization through the use of partial reconfiguration at its architectural level. Built within the DFG priority program 1148 Reconfigurable Computing its main goals are: • making partial reconfigurable designs viable for real-world applications, • operating system support for scheduling, placement and run-time reconfiguration of partially reconfigurable modules, • tool support for the development of run-time reconfigurable computation and communication modules using new inter-module communication para-digms, and to • provide a platform for interdisciplinary research on algorithms, methods, and applications using run-time reconfiguration. Its architectural support for partial reconfigurable modules simplifies the design and evaluation of modular and partially reconfigurable applications. Its key benefit is the decoupling of all peripheral I/O pins from the FPGA through the use of an external crossbar. This feature enables flexible signal routing to any reconfigurable region on the FPGA and effectively decouples the peripheral I/Os from the fixed FPGA pins. Moreover, it provides a flexible platform for run-time allocation models, real-time aspects and operating systems research for run-time reconfigurable systems. The design flow tool SlotComposer automates the creation of partially reconfiguration modules. It allows the automated insertion of inter-module communication structures. Moreover, it aids partial module placement with graphical visualization and creates design flow scripts for partial bitstream synthesis. As an application example using partial run-time reconfiguration, an advanced video application was implemented on the ESM platform. To support real-time video processing in the application, methods for hardware-software communication, hardware task placement, inter-module communication and decoupled peripheral I/O access were analyzed and implemented for use on the ESM platform.Partielle Rekonfiguration ist ein Spezialfall der FPGA-Konfiguration, bei der zur Laufzeit eine vordefinierte FPGA-Region mit einer neuen Schaltung geladen wird, während dabei die übrigen Regionen des FPGAs nicht gestört werden. Dies ist besonders erwünscht, wenn Geräte in einer kritischen Umgebungen arbeiten und ihr laufender Betrieb nicht unterbrochen werden darf. In diesem Fall erlaubt die partielle Rekonfiguration die Schaltungen von Teilsystemen im laufenden Betrieb auszutauschen, um die Effizienz und die Flexibilität der Schaltung, aufgrund von wechselnden Anforderungen oder variierenden Umgebungsfaktoren, zu verbessern. Die Verwendung der partiellen Rekonfiguration erhöht die Funktionalität und Flexibilität eines einzelnen FPGAs, so dass kleinere und somit günstigere FPGA-Bausteine verwendet werden können. Eingebettete Systeme mit FPGAs könnten damit im laufenden Betrieb an sich wechselnde Anforderungen in Echtzeit angepasst werden, wodurch die Implementierung verschiedener Anforderungen in einem einzigen Baustein zusammengelegt werden kann. Allerdings haben verschiedene Module unterschiedliche Anforderungen an die I/O- und Speicherschnittstellen, welche von aktuellen FPGA-Plattformen nicht berücksichtigt werden und damit die Entwicklung von rekonfigurierbaren Anwendungen erschweren. Diese Einschränkungen haben dazu geführt, dass im Bereich der partiellen Rekonfiguration nur wenige Beispiele die praktische Anwendbarkeit der partiellen Rekonfiguration zeigen. Die Erlangen Slot Machine (ESM) ist eine neuartige FPGA-basierte, dynamisch rekonfigurierbare Computerarchitektur, die für den Einsatz von partieller Rekonfiguration konsequent ausgelegt wurde. Ihre flexible Architektur vereinfacht die Entwicklung und Evaluierung von modularen und partiell rekonfigurierbaren Hardware-Designs. Ihr großer Vorteil ist die Entkopplung aller peripheren I/O-Pins durch den Einsatz einer externen Crossbar. Diese ermöglicht eine flexible Signalverteilung zu jeder rekonfigurierbaren Region auf dem FPGA, wodurch die peripheren I/Os von den physikalischen FPGA-Pins entkoppelt werden. Darüber hinaus bietet die ESM eine flexible Plattform für Entwicklung und Analyse von Scheduling, Platzierungsverfahren und Echtzeitbetriebssystemen für laufzeitrekonfigurierbare FPGA-Systeme im Allgemeinen. Mit dem Design-Flow Werkzeug SlotComposer wird die automatische Erstellung von partiell rekonfigurierbaren Modulen verwirklicht. Es ermöglicht das automatisierte Einfügen von Kommunikationsverbindungen zwischen partiellen Modulen, die graphische Platzierung von partiellen Modulen, als auch das Erstellen von Design-Flow Skripten für die Konfigurationsdaten-Synthese der partiellen Module. Als Anwendungsbeispiel für die partielle Rekonfiguration wurde eine erweiterte Video-Anwendung, die ein Assistenzsystem für die Erkennung von vorausfahrenden Fahrzeugen und Fahrbahnmarkierungen, auf der ESM-Plattform vollständig implementiert. Zur Unterstützung der Echtzeit-Videoverarbeitung mit partiell rekonfigurierbaren Videofiltern wurden Methoden für Hardware-Software-Kommunikation, Modul-Platzierung, Inter-Modul Kommunikation sowie Zugriff auf die I/O Pins der Peripherieschnittstellen entwickelt

Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine

We present an FPGA-based reconfigurable platform called Erlangen Slot Machine (ESM). The main advantages of this platform are: First, the possibility for each module to access peripherals independent from its location through a programmable crossbar, and local SRAM banks for individual modules. This physical design eases the implementation of run-time reconfigurable partial modules and enables an unrestricted relocation of modules on the device. We present our twoboard ESM implementation and demonstrate a partially reconfigurable video filter application as well as a relocatable computer game including a dedicated inter-module communication scheme

Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine

We present an FPGA-based reconfigurable platform called Erlangen Slot Machine (ESM). The main advantages of this platform are: First, the possibility for each module to access peripherals independent from its location through a programmable crossbar, and local SRAM banks for individual modules. This physical design eases the implementation of run-time reconfigurable partial modules and enables an unrestricted relocation of modules on the device. We present our twoboard ESM implementation and demonstrate a partially reconfigurable video filter application as well as a relocatable computer game including a dedicated inter-module communication scheme

Packet Routing in Dynamically Changing Networks on Chip

On-line routing strategies for communication in a dynamic network on chip (DyNoC) environment are presented. The DyNoC has been presented as a medium supporting communication among modules which are dynamically placed on a reconfigurable device at run-time. Using simulation, we compare the performance of an adaptive Qrouting algorithm to the well known XY-routing strategy. Both algorithms are adapted to support communication on the DyNoC which is equivalent to routing on meshes with obstacles. In our experiments, Q-routing proves its performance under varying network load while using only local information for its routing decisions

A Flexible Reconfiguration Manager for the Erlangen Slot Machine

We present a new concept as well as the implementation of a reconfiguration manager for a FPGA-based reconfigurable platform, the Erlangen Slot Machine (ESM). One main advantage of this platform is the possibility for each module to access its periphery independent of its location through a programmable crossbar, allowing an unrestricted run-time relocation of modules on the device. To aid the reconfiguration process we present a flexible plugin architecture for a hardware reconfiguration manager. Its advantage is fast preprocessing of bitstream data by different plugins such as a decompression and a relocation plugin. The plugin order is arbitrary and determined at run-time. Moreover, our architecture does not suffer from performance degradation if several plugins are cascaded

The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-Based Computer

Computer architects have been studying the dynamically reconfigurable computer [1] for a number of years. New capabilities such as on-demand computing power, self-adaptiveness and self-optimization capabilities by restructuring the hardware on the fly at run-time is seen as a driving technology factor for current research initiatives such as autonomic [2, 3] and organic computing [4, 5]. Much research work is currently devoted to models for partial hardware module relocation [6] and dynamically reconfigurable hardware reconfiguration on e.g., FPGAbased platforms. However, there are many physical restrictions and technical problems limiting the scope or applicability of these approaches. This led us to the development of a new FPGA-based reconfigurable computer called the Erlangen Slot Machine. The architecture overcomes many architectural constraints of existing platforms and allows a user to partially reconfigure hardware modules arranged in so-called slots. The uniqueness of this computer stems from a) a new slot-oriented hardware architecture, b) a set of novel inter-module communication paradigms, and c) concepts for dynamic and partial reconfiguration management

A dynamic noc approach for communication in reconfigurable devices

A concept for solving the communication problem among modules dynamically placed on a reconfigurable device is presented. Based on a dynamic network-on-chip (DyNoC) communication infrastructure, components placed at run-time on a device can mutually communicate. A 4x4 dynamic network-on-chip communication infrastructure prototype, implemented in an FPGA occupies only 7 % of the device area and can be clocked at 391 MHz